The invention relates to a method of synchronizing a binary data signal receiver and particularly has for its object to provide a method of synchronizing a receiver for demodulating a two-level quadphase coded data signal, this data signal comprising a first, a second, a third and a fourth equally long, consecutive half bit interval.
The invention further relates to a clock synchronization device for carrying out the method of synchronizing a receiver of a two-level quadphase coded data signal.
Quadphase coding is known from the article by U. Appel and K. Trondle: "Zusammenstellung und Gruppierung verschiedener Codes fur die Uebertragung digitaler Signale" published in the periodical Nachrichtentechnische Zeitschrift, Vol. 1, 1970, pages 11-16, FIG. 7 in particular. A quadphase coded signal is obtained by dividing a non-coded binary data signal into groups of two bits, denoted dibits. The first and the second bit, respectively, of the dibit is placed in the first and the second, respectively, half bit interval of the coded word and the inverted value of the first and the second bit, respectively, of the dibit is placed in the third and fourth, respectively, half bit interval of the coded word. The coding owes its name "quadphase" to the property that four elementary signals can be distinguished namely 0011, 1001, 0110 and 1100 (allotted to the dibits 00, 10, 01 and 11, respectively).